The personal computer and server industries may require performance gains across many workload types in order to be competitive. Various mechanisms are used to provide these levels of performance gains including, for example, core count increases and memory size/bandwidth/latency improvements. Memory improvements may take the form of faster Dynamic Random Access Memory (DRAM), higher Double Data Rate (DDR) bus frequencies, larger capacity Dual Inline Memory Modules (DIMMs), more DIMMs per channel and other optimizations. There are many DDR standards defined by the JEDEC Solid State Technology Association, such as, the Double Data Rate Fourth Generation (DDR4) Synchronous Random Access Memory (SDRAM) standard JESD79-4, published September 2012.
Higher DDR speeds require that DRAM channels be carefully tuned for optimum signal quality and DDR bus timing. This tuning is performed by the basic input/output system (BIOS) during boot up and is commonly referred to as “DDR training.” DDR training” includes many time consuming steps, for example, centering of various strobe signals, cross talk elimination and reference voltage calibration. These calibration steps are used to derive optimal DDR timing parameters that are applied to the DRAM controller and DIMMs. This programming is done before memory is accessed as these parameters cannot be updated during operation without disturbing memory traffic.
Non-optimum parameters result in higher bit error rates and generally destabilize system operation. These complex calibration steps result in increased boot time. Certain DDR proposals call for per DDR device calibration across multiple parameters to achieve higher speeds and lower voltages. As a result, memory training processes in these platforms may be increased.
In a typical memory system of a computer system, a memory controller facilitates the access of a memory module in the computer system. The memory module may include one or more memories. These one or more memories are also called ranks. The memory controller transmits a host of signals to the ranks including address signals, control signals, clock signals, etc., to access data from the ranks or to send data to the ranks. To send and receive correct data to and from the ranks, the memory controller trains (modifies) various signals with respect to a clock signal.
Typically, the memory controller may train a signal by transmitting a particular signal with respect to a clock signal to the ranks and then analyzing a response from each rank to ascertain if the rank correctly received the particular signal. Upon a correct response from the rank, the memory controller delays the phase of the particular signal with respect to the clock signal and then re-transmits the delayed particular signal with a delayed phase to the rank. The memory controller then analyzes a response from the rank to ascertain if the rank correctly received the delayed particular signal. If no response (or an incorrect response) is received from the rank to the memory controller, the memory module transitions to an unknown state.
Current DDR interfaces are achieving higher frequencies, and board routing flight times are not scaling with these frequencies, where board routing time is the time it takes for a signal to propagate along a particular signal route on a board. As a result, it is becoming more difficult to establish tight matching requirements between the control signals for the DDR bus relative to the clock signals.